1.AN65974 is written with GPIF configured for 32 bit interface. But when I open the GPIF II project of AN65974,it is in the 16 bit mode.And there is something in cyfxslfifosync.h.
/* 16/32 bit GPIF Configuration select */
/* Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 0 for 16 bit GPIF data bus.
* Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 1 for 32 bit GPIF data bus.
*/
So I define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (0).Is there something else for 16 bit mode set up?
2.I checked someting.I powered on FX3S first,and programed FX3S with loopback transfer img.then powered on FPGA.Afer several clocks,the FLAG[A:D] is 1001,and FPGA is in the 0 transfer mode(loop_back_idle).
After that I sent TEST.dat with the Control Center,and I checked FLAG signals and FPGA’s state machine for loopback transfer.The detail is below.
FLAGA: 1-1-1-1-1-1-1-1-1-1
FLAGB: 0-0-0-0-0-0-0-0-0-0
FLAGC: 0-1-1-1-1-1-1-1-1-1
FLAGD: 1-1-1-1-1-0-0-0-0-0
state machine of FPGA: 0-0-1-2-3-3-4-5-6-7
And the Control Center box said BULK OUT transfer completed.But when I transfer data in with Control Center,and it failed.The Control Center box said BULK in transfer failed with error code:997.I think the reason is FLGAB can’t change to 1 from 0,is it?How can I do next?
3.Our FPGA is not Altera or Xilinx,it is Actel’s AGL250V5-FG144I.In this platform, it has not the DDR modern,and we made it.The function of ddr is only to reverse the clock,is it?