GPIF Timing

Hi,

I am designing a GPIF interface and would like to use the Timing window of the GPIF II Designer tool.

On my write scenario, master writing to slave, FX3 performing IN_DATA operation, I seems to have my input ( EN signal and DataBus ) 10ns early. Is that expected in hardware of is it a error in the timing windows ?

My state should transition from OP_WAIT to WR_TGT upon EN signal. The timing windows shows EN transition 10ns earlier. The DataBus is sample during WR_A2U_TH0. I have transition occurring in states before.

My understanding is that those transitions should occurs one cycle later.

Regards,
Stan